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subTask 1.6(UPV): Techniques for reducing energy consumption in interconnection networks

Leader: Vicente Santonja; Researchers: Marina Alonso, Salvador Coll, Juan Miguel Martínez, Pedro López

1. Brief Description of the Goals

Power consumption reduction techniques are being increasingly used in computer systems, and high-performance computing systems are not an exception. In particular, the power consumed by the interconnection network circuitry has a significant contribution to the total system budget. Fat-tree interconnection networks are one of the most popular topologies due to their high bisection bandwidth and ease of application mapping for arbitrary communication topologies. Most applications have communication topology requirements that are far less than the total connectivity provided by fat-trees. Applications that scale most efficiently to large numbers of processors use point-to-point communications patterns where the average number of distinct destinations is relatively small. This provides strong evidence that many application communication topologies exercise a small fraction of the resources provided by fat-trees. Moreover, traffic in an interconnection network exhibits large spatial and temporal variance, leading to inactivity periods at several links in the network. On the other hand, fat-trees are particularly well-suited for applying power consumption reduction techniques since they provide multiple alternative paths for each source/destination pair

Several power reduction techniques for interconnection networks have been proposed based on Dynamic Voltage Scaling (DVS). DVS was originally proposed, and now is widely deployed, for microprocessors. When applied to networks, this approach allows DVS links to work in a discrete range of frequencies and supply voltages, which leads to different levels of power consumption in response to their traffic utilization. DVS has significant drawbacks: it requires a sophisticated hardware mechanism to ensure correct link operation during scaling, it consumes significant CMOS area, and DVS links continue to consume power even while idle.

This task explores the opportunities to reduce power consumption by dynamically switching on/off links based on the traffic they support while running a set of applications.

2. Scientific and Technical Developed Activities

We have developed a novel technique to reduce power consumption in fat-tree interconnection networks. Two important contributions of our mechanism are its simple implementation and the fact that the underlying routing algorithm does not need to be modified. The mechanism can be set to provide different levels of sensitivity to traffic variations. Moreover, power reduction policies with different levels of aggressiveness can be set, too. Hence, different ratios of power saving versus performance penalty can be obtained. Another significant contribution is the improvement of our original mechanism implementation by defining a dynamic behavior of the thresholds that control the mechanism operation. The dynamic version of the mechanism significantly outperforms the static approach at no additional performance cost.

Our results, published by Alonso et al. in HPCC 2007, show that significant power savings can be obtained with moderate latency penalty, by selecting a conservative power reduction policy. Additional power savings can be obtained by further stressing the network at the cost of increasing latency.  

On the other hand, in Alonso et al. in Parallel Computing Journal 2010, a similar mechanism for power saving in regular interconnection networks was published. Finally, part of the work performed in this subTask has lead to the presentation and defence of the PhD thesis of M. Alonso, in June 2012.

Publications: [alonso07a ], [alonso07b ]

Projects funded by Public Calls:  TIN2006-15516-C04-01TIN2009-14475-C04-01

External collaborations Academia: --

External collaborations Industry: --

Company Agreements: --

PhD dissertations: Marina Alonso Díaz

Patents: --