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subTask 2.1(UPV): Analysis of on-chip interconnection network topologies

Leader: M. Engracia Gomez; Researchers: Francisco Gilabert, Pedro López

1. Brief Description of the Goals

Mesh 2-D is the typical topology used in NoCs, nevertheless its scalability is limited considering the current and future core counts. The 2-D mesh bisection bandwidth does not scale at the same speed as the number of cores in chips. This means that new topologies are required at the NoCs to improve bandwidth and latency. But this performance improvement must be got considering other network design parameters, that is, without increasing significantly the area and power consumptions, which are two critical factors in NoCs. The aim of this task is the proposal and evaluation of new topologies for NoCs that consider these issues.

2. Scientific and Technical Developed Activities

This task has explored different NoC topologies that have been evaluated having in minded the three design parameters of NoCs: performance, area and power. 

Before giving more resources to the network we have analyzed and evaluated to reduce the number of resources available in the NoC by associating more than one core to the same router. The aim is to reduce the area and power used by the NoC while reducing the network latency. This approach is very interested for those applications that do not require high bandwidth but low latency.

Second, for those applications that are bandwidth demanding, we have evaluated the use of topologies different to the 2-D mesh. In particular we have considered multidimensional topologies and fat-trees. For both of them, beside performance models, also area and power models have been developed in order to allow evaluating them from both, from a performance point of view and from a consumption point of view. 

Finally in this task also the implications of VCs in the NoC has been evaluating, proposing to use parallel switches instead of a switch with different queues with the aim of doing a more efficient implementation for NoCs.

Results of this work proposing multidimensional topologies for the implementation of NoCs were published by Gilabert, et al. in NOCS 2008. Results evaluating fat-trees were published by Ludovici et al. in DATE 2009. More detailed evaluations of multidimensional topologies were published by Gilabert et al. in CISIS 2009 and published by Gilabert et al. in Embedded Systems Design and Verification 2009. The proposal and evaluation of VCs in NoCs were published by Gilabert et al. in NOCS 2010. Finally the tool implemented for exploring the topology design space was published by Sonntag et al. in ICCAD 2010. 

Publications: [Gila07a], [Gila07b] [Gila08a], [Meda08], [Gila08b] [Gila09a], [Ludo09a], [Gila09b], [Ludo09b], [Gila09c]

Projects funded by Public Calls: TIN2006-15516-C04-01,  TIN2009-14475-C04-01STREP num. 288574 PAID-06-10 (2370)

External collaborations Academia: David Bertozzi´s Group

External collaborations Industry: --

Company Agreements: --

PhD dissertations: Francisco Gilabert Villamón

Patents:  --