Home  
 

Main Menu
Home
About us
Project Description
Quantitative Results
Research Lines
Research Results
Impact on Society
Press room
Contact us
News
Secure Login
Events Calendar
« < October 2017 > »
M T W T F S S
25 26 27 28 29 30 1
2 3 4 5 6 7 8
9 10 11 12 13 14 15
16 17 18 19 20 21 22
23 24 25 26 27 28 29
30 31 1 2 3 4 5
Login

subTask 2.4(UPV): A new switching strategy design (Virtual Virtual Channels)

Leader: M. Engracia Gomez; Researchers: Crispín Gómez, Pedro López

1. Brief Description of the Goals

One of the main particular features of Networks-on-chip  (NoC) comparing with off-chip networks is that buffers are a resource that must be used in a restrained way since they consume a large percentage of the area and power of a NoC, and moreover they limit the network working frequency. However, inside the chip, wires do not have the limitations existing outside the chip; wires can be used with much less limitations. In this task we propose a NoC without buffers, with the aim of increasing the network frequency and reducing the area and power consumptions. The proposal is that wires store the data. The problem to be solved is that wires opposite to buffers do not store data for an indefinite period; wires maintain data while they are transferred through them from one end to the other one. When a packet reaches the other end, it needs another wire to be stored. If there is no wire available, the packet is discarded. In order to avoid losing packets, we have introduced acknowledgments and retransmissions of packets. Moreover, in order to increase the probability of finding an available wire, we propose to use adaptive routing and exploit the NoC high wiring capability using several parallel links in the same direction. On the other hand, when a packet arrives into a switch, it must have an available routing circuit that allows it to get an output port; otherwise the packet will be discarded. So we have considered as many routing circuits as input ports at the switch.

2. Scientific and Technical Developed Activities

The aim of this task was to design a switch architecture with low buffer requirements. Buffers are the main contributors to power and area consumptions in NoCs. To reach this aim, we have proposed to remove buffers in the NoC switches. This have significantly contributed to reduce both area and energy consumptions, but at the same time has introduced the problem of no having a place where packets can wait the resources they next need. If there are no buffers, packets cannot wait and they must be dropped when the resource they need is busy serving another packet.

To avoid discarding packets in these topologies without buffers, new mechanisms to avoid packet dropping had been designed based on ack and nack messages and the use of parallel links that can help having available resources. Additionally these bufferless NoCs have been enhanced with other mechanisms trying to reach the maximum performance of the NoC while introducing negligible complexity. As the evaluation results show, the proposed mechanisms obtain better performance results that wormhole that is the switching technique commonly used in NoCs. 

Results evaluating parallel links in NoCs with buffers were published by C. Gómez et al. in PDP 2008 Conference. The proposal of the bufferless network with ack and nack  was published by C. Gómez et al. in ICPADS 2008 Conference. The mechanisms that enhance the previous proposal to try to maximize performance were published by C. Gómez et al in Euro-Par 2008 Conference (Best Paper award). Moreover, a journal paper has been published by C. Gómez et al. in Concurrency and Computation: Practice and Experience, vol 23, issue 11, 2011, as an extension of the Euro-Par paper.


Publications: [Gome08a], [Gome08b], [Gome08c], [Gome08d], [Gome08e], [Gome08f]

Projects funded by Public Calls:  TIN2006-15516-C04-01,  TIN2009-14475-C04-01STREP num. 288574 PAID-06-10 (2370)

External collaborations Academia: --

External collaborations Industry: --

Company Agreements: --

PhD dissertations: Crispín Gómez Requena

Patents: --