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subTask 2.5(UPV): Techniques for routing and power saving in NoCs

Leader: José Flich; Researchers: Andrés Mejía, Samuel Rodrigo, Jesús Camacho, José Cano

1. Brief Description of the Goals

The main goal of this task is to develop new implementations for routing algorithms in on-chip networks. On-chip networks is a new research field (started in 2001) having many researchers working on. Indeed, a network inside a chip is challenging since strict constraints in power and area budget must be enforced by the provided solutions.

The routing implementation to cover manufacturing defects and new properties (like virtualization or voltage/frequency islands) require efficient solutions, since having a complete routing table at each switch or end-node (current solutions used in off-chip networks) is not appropriate. In this task we target the achievement of an efficient (low area requirements, low power requirements) implementation of most routing algorithms for on-chip networks.

2. Scientific and Technical Developed Activities

Two main implementations strategies have been followed. The first one is called Region-based Routing (RbR). In RbR many routing entries of a switch (each one for a particular destination) are packet in a so-called region. That region has the property that all the nodes in the region are reached through the same output port at a given switch, so the representation of the region can be reduced to two simple coordinates. By doing this, the routing table is largely reduced and therefore, less area requirements are needed.

RbR has been presented in several top-ranked conferences in the field and in top-ranked journals like one published by Mejia in Transactions on VLSI 2009. In addition, RbR has been linked to the SR routing algorithm (see task 1.2) and both (RbR and SR) are the key topics of a defended PhD dissertation by Andres Mejía. Also, RbR has been linked to the APSRA method (a partly adaptive routing algorithm).

The second implementation, referred to as Logic-Based Distributed Routing (LBDR), is more aggressive, in the sense that all the routing information is packed into few bits per switch (8 bits the most simple solution) and few logic gates. This mechanism requires, thus, a very small area in the switch, however is able to support most routing algorithms in a network with manufacturing defects.

LBDR has been presented in top-ranked conferences and journals as well, as has been used as a link in the collaboration with different entities, like University of Ferrara (internships have been done with HiPEAC), Simula Research Lab. Also, LBDR is being considered by the European project GALAXY, and is one central component in two European Projects: CA501 COMCAS label and NaNoC with nº contract 248972. Intel is also considering its use in their research activities, and probably on its final products. 

Recently, LBDR has also been enhanced with collective communication support and the possibility to define regions that isolate traffic. This latter property enables the concept of virtualization. Also, a reduced version (called FDOR) with fewer properties has been proposed. Several publications with improvements of the basic mechanism have been achieved, published by Rodrigo et al. IEEE Computers & Digital Techniques, Vol. 3, 2009, published by Rodrigo et al. ACM/IEEE International Symposium on Networks-on-Chip 2010 conference and published by Rodrigo et al. in IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 30, 2011. 

Finally, extension of the LBDR concept to irregular topologies has been analyzed and proposed in collaboration with ST Microelectronics (France). A patent titled “Switches and a Network of Switches” has been filled protecting the mechanisms. Several publications have been achieved published by Cano et al. in NOCS 2011 conference, published by Dubois et al. in NOCS 2011 conference and one accepted publication in Transactions in Computers for 2013. 

Publications: [Flich09] [Rodrigo08] [Frank09] [Rodrigo09] [Rodrigo08b] [Flich08] [Flich08b] [Flich08c] [Flich08d] [Flich07] [Mejia09] [Mejia07] [Tornero08] [Mejia08]

Projects funded by Public Calls:  TIN2006-15516-C04-01TIN2009-14475-C04-01STREP Num. 248972 , CA501 COMCAS label , TSI-020400-2009-64 , PRI-PIBIN-2011-0989 , PCC-08-0078-9856 

External collaborations Academia: Shashi Kumar, Jönköping University (Sweden)

External collaborations Industry: AMD (US)Intel (US)ST Microelectronics (France)

Company Agreements: --

PhD dissertations:  Andrés Mejía GómezSamuel Rodrigo MocholíJesús Camacho Villanueva