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subTask 2.6(UPV): Communication-aware topological mapping technique for NoCs

Leader: Juan Manuel Orduña; Researchers: Rafael Tornero

1. Brief Description of the Goals

The existing topological mapping proposals for NoCs usually consider regular topologies like 2-D meshes. The reason is that these topologies offer low and constant link delay. However, manufacturing defects or even real-time failures often make the resulting network topology to become irregular, and some routing techniques has been proposed for solving these problems. Additionally, there are also NoCs with inherent irregular topologies, and the methodology used in the design flow can also introduce some irregularities. These scenarios show the need for a topological mapping technique that can adapt the communications exchanged by the IPs to the existing network topology, regardless of the network regularity. Such a topological mapping technique would help to reduce network latency and power consumption. 

2. Scientific and Technical Developed Activities

The primary and main aim of this research line was the development of a topological mapping technique fulfilling the aforementioned requirements. In order to achieve this goal, we developed a topology-independent mapping technique that globally adapts the communication pattern generated by the IPs to the available network bandwidth in the different parts of the network. Unlike other mapping techniques, the proposed method uses an abstraction of the network (a table of communication costs) as the model for both the NoC topology and the routing algorithm (the network resources). In this way, the method can be used with either regular or with irregular topologies, and with any routing algorithm (different topologies and/or routing algorithms are modeled as tables with different values). This feature can help to fully exploit irregular NoCs, provided that the routing function provides alternative paths for reaching the destination. Results showed that the proposed technique can provide better performance than other mapping techniques, not only in terms of average latency but also in terms of power consumption. On other hand, since the underlying methodology is based on correlating the network model, the proposed technique does not need to experimentally test each solution considered, requiring a relatively low computational effort. These results were published by Tornero et al. in HiPEAC 2008 conference workshops, by Tornero et al. in the Euro-Par conference, 2008 and by Tornero et al. in Computing and Informatics, Vol. 31, 2012.  

The proposed technique was jointly applied to a new topology-agnostic routing technique in order to improve the performance for application-specific NoCs with any network topology, published by Tornero et al. in 11th EuroMicro Conference on Digital System Design (2008) and by Tornero et al. in International Journal of Parallel Programming Vol. 39, n. 3, 2011

Also, we adapted, together with Jönköping University (Sweden), the mapping technique to NoCs using source routing, with the purpose of limiting the path lengths for inter-core communication. The results were published in the Euro-par 2009 conference workshops by Tornero et al. in Workshop on HPPC 2009.

On other hand, we integrated the topological mapping technique with the APSRA methodology developed by University of Catania, improving latency and fault tolerance, published by Tornero et al. in Journal of Universal Computer Science, vol. 18, no. 7 (2012), by Tornero et al. in the IPDPS Conference Workshops, 2009 and by Tornero et al. in the IPDPS Conference Workshops, 2010.

Publications: [Torn08a], [Torn08b], [Torn08c], [Torn09], [Torn08d],[Torn09b], [Torn09c], [Sori09]

Projects funded by Public Calls:  HiPEAC by european grants, TIN2006-15516-C04-04 , TIN2009-14475-C04-04,  TIN2007-29664-E  by  national grants.

External collaborations Academia: Vincenzo Catania y Maurizio PalesiShashi Kumar

External collaborations Industry: --

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