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Task 3 (UPV): Improving microprocessor performance

Leader: Julio Sahuquillo; Researchers: Rafael Ubal, Noel Tomás, Salvador Petit, Pedro López

subTask 3.1 Design of techniques for reducing cache power consumption

subTask 3.2 Design of cache memories with backup cells

1. Brief Description of the Goals

Current research in high-performance microprocessors is mainly focusing on the reduction in power consumption while maintaining the performance instead of trying to further improve the performance. In other words, although single core performance is important, power and thermal issues are mainly driving current microprocessor design. Research efforts have been addressed to mainly reduce to kinds of power: static and dynamic. Static power or leakage is proportional to the number of transistors implemented in the microprocessor component while dynamic power rises when transistors change their state. In addition power is not distributed uniformly across the chip area but on specific structures, that is, the different microprocessor structures present different power densities. Components with the highest power density are referred to hot spots and must be addressed in order to reduce package and cooling costs.

In this research line we have addressed both the reduction of static energy, global energy and hot spots while maintaining the performance of high-performance microprocessors.

2. Scientific and Technical Developed Activities

Static is a major design concern in current processors. Research in this activity, concentrate on caches, since these memory structures occupy an important percentage of the total die area. We have developed an extensive and fruitful research on these topics. We implemented in a detailed cycle-by-cycle application driven processor simulator many models of innovative cache structures. The research has proposed for the first time heterogeneous microprocessor structures that have been followed by other researchers to develop other structures (e.g. register files for fine-grain multithreaded processors). Originally, we call to this design macro-cell, since we designed a big cell consisting of a set of bits implemented with different technologies (i.e. SRAM and eDRAM). SRAM was adopted for performance and eDRAM for energy. To carry out this research, we modelled our proposals or specific components of it in the three major simulators: Simplescalar simulator for detailed execution time, CACTI for area and energy, and PSPICE for checking the electrical behaviour.

Results of this work has been published by Valero et al. in MICRO 2009 conference, and an extension of that work addressing performance in IEEE Transactions on Computers, vol. 61, issue 9, 2012. In addition, the design was extended to address technological concepts, e.g. required capacitors to avoid performance losses as well as a detailed energy study. Results of this work were published by Valero et al. in IEEE Transactions on VLSI, vol. 20, issue 6, 2012. To avoid manufacturability constraints that can yield to area wasting, we designed heterogeneous caches at the bank granularity. Results of this work were published by Valero et al. at ICCD 2012.

This task has also focused on new replacement algorithms for L2 caches, since performance of these caches highly impact on the microprocessor performance due to the huge latency of accessing main memory. We devised a new algorithm that improves the performance of current proposals. Results of this work has been published by Valero et al. in PACT 2011 conference, and an extension of that work considering a victim cache in the TACO journal, vol 9, issue 3, 2012.

In addition, research work has been done performing on register renaming techniques. This work focused on energy and area. To this end, unlike conventional approaches we combined both a CAM and an SRAM table. Results of this work have been published by Petit et al. in ICCD 2009 and an extension has been accepted for publication in IEEE Transactions on VLSI.

Publications: [Sahuquillo07], [Ubal07d], [Tomas08], [Ubal09b], [Valero09]*, [Petit09]*

Project funded by Public Calls:  TIN2006-15516-C04-01,  TIN2009-14475-C04-01  TIN2008-05338-E/TIN,  PAID-06-07-3281GV/2009/043 

External collaborations Academia:  Pierfrancesco Foglia

External collaborations Industry: --

Company Agreements: --

PhD dissertations: --

Patents: --