Main Menu
About us
Project Description
Quantitative Results
Research Lines
Research Results
Impact on Society
Press room
Contact us
Secure Login
Events Calendar
« < October 2017 > »
25 26 27 28 29 30 1
2 3 4 5 6 7 8
9 10 11 12 13 14 15
16 17 18 19 20 21 22
23 24 25 26 27 28 29
30 31 1 2 3 4 5

Task 4 (UPV): Processor architectures for embedded real time systems

Leader: Julio Sahuquillo; Researchers: Diana Bautista, Houcine Hassan, Salvador Petit

1. Brief Description of the Goals

High-performance microprocessors, e.g., multithreaded and multicore processors, are being implemented in embedded real-time systems because of the increasing computational requirements. These complex microprocessors have two major drawbacks when they are used real-time systems. First, their complexity difficult the calculation of the WCET (Worst Case Execution Time); second, power consumption requirements are much larger, which represents a major concern in these systems.

To deal with consumption, many systems apply Dynamic Voltage Scaling (DVS) techniques which dynamically change the system speed depending on the workload characteristics. DVS costs in a multicore system can be reduced if different cores share the same DVS regulator. In this context, to handle energy efficiently, the workload must be properly balanced among the cores.

The research performed on this line has addressed multicore multithread processors sharing a global  DVS which was a major concern several years ago, since in this way  complexity and power distribution can be largely reduced. We have mainly investigated and proposed novel partitioning heuristics, that is, heuristics aimed at distributing the workload among cores in order to allow the system to work with the lowest frequency/voltage level while satisfying the real-time constraints. 

2. Scientific and Technical Developed Activities

The work performed in this research line can be broken down in two main groups attending to the characteristics of the real time system being designed, i.e., soft real-time and hard real-time. All this work has been performed on an extended version of the Multi2Sim simulator that was tailored to deal with real time constraints as well as to allow a given task to enter and leave the system more than once during a given hyperperiod. In addition energy results were also estimated.

Regarding the first group, we proposed a novel soft power-aware real-time scheduler for a state-of-the-art multicore multithreaded processor. The proposed scheduler make uses of DVS techniques to reduce the energy consumption while satisfying the constraints of soft real-time applications. Results, which provided significant energy savings, were published by Bautista et al. in the IPDPS 2008 conference. 

We also devised an algorithm to partition the workload attending to the memory requirements of the different benchmarks. These results were published by Diana et al. in the ICS 2009 conference. An extension of the previous of the previous work considering soft and hard real-time tasks was published by March et al. in Computer Journal, vol 54, issue 8, 2011. Finally, we also have dealt with task migration and QoS in soft real-time tasks. These results have been published by March et al. at the Euro-Par conference.

Publications: [Bautista08a], [Bautista08b], [Bautista09

Projects funded by Public Calls: TIN2006-15516-C04-01,  TIN2009-14475-C04-01  TIN2008-05338-E/TIN,  PAID-06-07-3281GV/2009/043 

External collaborations Academia: --

External collaborations Industry: --

Company Agreements: --

PhD dissertations: --

Patents:  --