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subTask 1.3 (UM): Energy-efficiency in processor cores, memory and interconnection network

Leader: Juan L. Aragón; Researchers: Antonio Flores, Juan Manuel Cebrián, Manuel E. Acacio, José M. García

There is a modification within subTask 1.3 (UM): Energy-efficiency in processor cores, memory and interconnection network. In particular, subTasks 1.3.3 and 1.3.4 have been joined into a unique subTask since there were high similarities between the two of them. For this reason, it is not convenient to continue with the two subTasks split independently. In order to reflect this change, subTask 1.3.3 has changed its original name to: Design of mechanisms for reducing the energy consumption of the interconnection network in a scalable CMP architecture. The goals of the new joint subTask are the same as proposed in the original project memory.

1. Brief Description of the Goals

The main goal of this task is the development of novel energy-efficient approaches aimed at efficiently managing the correct thermal operation of the processing cores of a CMP. These are key design aspects for next-generation and dense CMP architectures that will implement a high number of cores. Furthermore, the static power (or leakage) dissipation of the processing cores as well as caches, which strongly depends on the building process technology, will be one of the major design concerns for future CMP architectures (built on deep submicron process technologies: <32nm). In this scenario, both energy consumption and power dissipation on the many processing cores could be so high that all the cores could not work simultaneously at full speed during a long period of time without temperature reaching non-tolerable levels that would cause chip malfunction.

2. Scientific and Technical Developed Activities

At the interconnection network level (subTask 1.3.3 “Design of mechanisms for reducing the energy consumption of the interconnection network in tiled CMP architectures”), we have first developed a simulation framework for measuring and evaluating the energy-efficiency of a CMP processor with special emphasis on the interconnection network. This simulator was presented and published by Flores et al in 2007 SEC Conference. After that we proposed several techniques based on the use of heterogeneous networks (in different metal layers) with different physical properties, bandwidth, latency and power dissipation in order to reduce the overall interconnect power and energy consumption in tiled CMPs. Our first proposal sends critical and short messages through low-latency wires whereas non-critical and long messages are sent through low-power wires. The main research results were published by Flores et al in 2007 HiPC Conference. Another proposal consisted of applying an address compression scheme that dynamically compresses the addresses within coherence messages allowing for a significant area slack. The arising area is used for exploiting wire latency, therefore, improving performance and energy consumption. The main research results were published by Flores et al in 2008 ICPP Conference. Finally, we have proposed a novel pre-fetching mechanism in the context of heterogeneous interconnects that will use the low-energy wires for pre-fetching purposes while not degrading performance by using the low-latency wires for critical messages. The main research results were published by Flores et al in 2010 EUROMICRO-PDP Conference. As a side note, this research of energy-efficient approaches for reducing the energy consumption of the interconnection network in tiled CMP architectures has resulted in the PhD Thesis of Antonio Flores. In addition, other research results were published in the following journals: Flores et al. in The Journal of Supercomputing, vol. 45, no. 3, 2008; Flores et al. in Journal of Systems Architecture, vol. 56, no. 9, 2010 and Flores et al. in IEEE Transactions on Computers, vol. 59, no. 1, 2010.

Regarding the task on energy-efficiency, at the core level (subTask 1.3.1 “Energy- and Temperature-aware processing core design”) we have proposed different approaches within this research project. A first proposal was aimed at reducing the static power (leakage) of traditional value predictors with a minimum impact on their prediction accuracy for deep submicron process technologies (lower than 90nm). The research results were published by Cebrian et al. in HP-PAC 2007 Workshop; by Cebrian et al. in Computing Frontiers (CF) 2010 Conference; and by Cebrian et al. in The Journal of Supercomputing, vol. 55, no. 1, 2011.

A second proposal was aimed at reducing the energy consumption of the instruction cache by determining the instructions within a cache line that will be used the next fetch cycle and accessing only those useful instructions of the line.  The research results were published by Aragon et al. in Journal of Systems Architecture, vol. 54, no. 12, 2008.

We also proposed a novel mechanism aimed at applying energy-efficient microarchitectural policies under power constraints, in order to meet a limited peak power budget that cannot be exceeded, at minimal performance cost contrary to DVFS-based approaches that either degrade performance too much or does not meet the power budget accurately. We called this proposal the Power-Token approach that dynamically estimates the processor power consumption at a cycle-level in order to select the most appropriate power-saving microarchitectural technique to accurately match a temporary power constraint. The initial results were focused on single-core processors and were published by Cebrian et al. in IPDPS 2009 Conference.

We later focused on a tiled CMP environment running parallel applications where DVFS-based approaches incur even in more severe performance degradation due to synchronization points. In a CMP scenario we proposed Power Token Balancing an approach that monitors the CMP global power budget in a way that when there are cores under their local power budget they can give their exceeding power tokens to cores over their local power budget (critical threads) so the latter can continue their execution without any delays in order to not degrade to global performance of the parallel application while at the same time guarantying the global power budget is not surpassed. The results were published by Cebrian et al. in IPDPS 2011 Conference and by Cebrian et al. in Computing, [DOI: 10.1007/ s00607-012-0236-6], 2012.

Finally, we explored the design of low-power techniques and hot-spot detection mechanisms for 3D-stacked processors. 3D-stacked architectures have emerged as a novel design technology that has the potential to address many of the problems of future high-performance multicore processors. While 3D integration provides increased transistor density and reduced wires, which results in faster on-chip communication and lower power, however, stacking multiple dies introduces serious thermal challenges due to the higher power density which not only exacerbates existing hotspots but can create new ones. In this context, we proposed a new power balancing policy between the different core layers that takes into account temperature and layout information to balance the available power per core along with other power specific optimizations for 3D designs. The results were published by Cebrian et al. in Euro-Par 2011 Conference. As a side note, this research has resulted in the PhD Thesis of Juan Manuel Cebrian.


Publications: [Flores07a], [Flores07b], [Cebrian07a], [Cebrian07b], [Flores08a], [Flores08b], [Aragon08] and [Cebrian09].

Projects funded by Public Calls:  TIN2006-15516-C04-03 and 05831/PI/2007.

External collaborations Academia: Stefanos Kaxiras, Yiannakis Sazeides

External collaborations Industry: --

Company Agreements: --

PhD dissertations: Antonio Flores GilJuan Manuel Cebrián González.

Patents:  --