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Activity 1: Out-of-order commit without checkpointing

 Leader: Julio Sahuquillo; Researchers: Rafael Ubal, Salvador Petit, Pedro López

1. Brief Description of the Goals

Current superscalar processors commit instructions in program order by using a reorder buffer (ROB). The ROB provides support for speculation, precise exceptions, and register reclamation. However, committing instructions in program order may lead to significant performance degradation if a long latency operation blocks the ROB head.

Several proposals have been published to deal with this problem. Most of them retire instructions speculatively. However, as speculation may fail, checkpoints are required in order to rollback the processor to a precise state, which requires both extra hardware to manage checkpoints and the enlargement of other major processor structures, which in turn might impact the processor cycle.

This research line focuses on devising new processor architectures to allow out-of-order commit in a nonspeculative way, thus avoiding checkpointing. The work has focused in three main processor architectures: superscalar, multithreaded, and multicore, improving the performance in all of them while reducing the hardware complexity.

2. Scientific and Technical Developed Activities

In this activity we developed the Multi2Sim simulador (www.multi2sim.org/), a simulator framework that is currently widely used through the scientific community around the world. This simulator framework models multithreaded and multicore processors, as well as, GPGPUs. This year a tutorial about it will be given at ISCA 2013 conference. Moreover, companies, like AMD and Nvidia, have participated in the development of the GPU part of the simulator and are highly interested on its use. These reasons, lead us to consider this open source framework as one of the main achieved results in this task.

During this activity, the baseline simulator was extended modify the conventional microprocessor architecture in order to support out-of-order retirement of instructions. More precisely, we devised the out-of-order commit VB (validation buffer) architecture and evaluate it on this framework. This architecture replaces the ROB with a buffer that keeps dispatched instructions until they are nonspeculative or misspeculated, which allows an early retirement.  By doing so, the performance bottleneck is largely alleviated. However, different microarchitectural mechanisms, like register renaming must be re-designed. The main results of this work were published by Ubal et al. in IEEE Transactions on Computer vol. 15, no. 12, 2009 and in the PACT 2007 conference.

Due to its advantages on performance and power compared to conventional processor microarchitectures, we adapted our idea to multithreaded processors and multiprocessor systems. The main results on multithreaded processors were published by Ubal et al. in the IPDPS 2008 conference. Results dealing with memory consistency on multiprocessor systems were published by Ubal et al. in IEEE Transactions on Parallel and Distributed Systems vol. 23, no. 8, 2012. 

Finally, the research carried out in this task has been also published as the PhD Thesis of Rafael Ubal, currently hired at the Northeastern University of Boston with David Kaeli.

Publications: [Ubal07a], [Ubal07b], [Ubal07c],  [Ubal08 ], [Ubal09a] and [Ubal09b]*

Projects funded by Public Calls: TIN2006-15516-C04-01,  TIN2009-14475-C04-01  TIN2008-05338-E/TIN,  PAID-06-07-3281GV/2009/043 

External collaborations Academia: David Kaeli

External collaborations Industry: --

Company Agreements: --

PhD dissertations: Rafael Ubal Tena

Patents: --