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Technology Transfer Results
  • Set-up of a direct path for technology transfer to top information technology companies (AMD, Sun Microsystems, HP) through membership to the HyperTransport Technology Consortium (HTC), membership to the HTC Technical Working Group (the committee that makes decisions on standardization of HyperTransport technology), and leadership of the HTC Advanced Technology Group (the committee that proposes technology to standardize, in addition to the HTC member companies). We have contributed to the definition and development of the following standards:
  1. High Node Count HyperTransport Specification 1.0, approved by the HyperTransport Technology Consortium on Feb. 11, 2009.
  2. HyperTransport Node Connector Specification and HyperTransport Mezzanine Connector Specification, approved by the HyperTransport Technology Consortium on Nov. 23, 2009 and Dec. 2, 2009, respectively.
  3. HyperTransport Over Ethernet Specification (HToE), approved by the HyperTransport Technology Consortium on Sept. 23, 2010
  4. HyperTransport Over InfiniBand Specification (HToIB) approved by the HyperTransport Technology Consortium on Feb. 28, 2011.
  • Set-up of a shared-memory cluster prototype with 1024 cores and FPGA-based network interfaces to implement and evaluate HyperTransport extensions on FPGAs, as well as the scalability of shared-memory architectures and associated software. Its unique feature is that cache coherence protocols are constrained to each individual motherboard while cores are able to access memory from any node. This way, scalability is dramatically enhanced with respect to existing shared-memory architectures. Correctness is ensured by exclusively assigning each memory region to a single coherence domain. We have successfully run the PARSEC and SPLASH benchmark suites using only remote memory (from other cluster nodes). Also, we have ported a multi-entry MySQL server, using the shared memory to store an in-memory database, achieving up to 75X speedup.
  • Set-up of a battery-less wireless sensor network (WSN) prototype with solar cells and an ultracapacitor for energy harvesting and storage. We have shown the feasibility of ensuring long-lasting operation of low-power sensor nodes, such as the Telosb, by adapting the duty cycle of the radio of the wireless node to the charge/discharge cycles of the ultracapacitor.
  • Set-up of a detailed simulation tool for InfiniBand using the OPNET Modeler software, published in OPNET support center and used by researchers from MITRE Corporation.
  • Set-up of several research lines related to server components, infrastructure, and applications that led to the following results, among others:
  1. A very flexible, partitionable, fault-tolerant, area and power efficient unicast and broadcast routing algorithm for networks on chip, in collaboration with AMD. This routing algorithm was later implemented by Intel on FPGA after publication. Extended to support manufacturing defects.
  2. A complete characterization of on-chip communication and synchronization primitives and a set of programming guidelines for dual Cell-based blades.
  3. A cost-effective fault-tolerant cache coherence protocol that tolerates packet losses without introducing race conditions
  4. A very simple and efficient deterministic routing algorithm for fat trees (patented in US). Sun Microsystems InfiniBand Magnum switch (3456 ports, the largest in the world) implements a fault-tolerant, partitionable version of this algorithm
  5. A new patent on a technique named RECN (Regional Explicit Congestion Notification), that eliminates the head-of-line blocking and performance losses produced by congestion trees (patented in US and Great Britain jointly with Xyratex).
  6. The first dynamic reconfiguration algorithm for high-speed interconnection networks with source routing, in collaboration with Simula Research Laboratory.
  7. A hybrid n-bit macrocell combining SRAM with DRAM technology, proposed for L1 n-way set-associative caches, that drastically reduces leakage power consumption.
  8. A simple and low-cost replacement policy for last level caches that takes into account recency of information. The proposed policy improves the system performance over existing strategies.
  9. A scheduler for real-time tasks in multicore systems implementing DVFS mechanisms to highly reduce the energy consumption while guaranteeing the real-time constraints of the workload.
  10. A dynamic power-aware partitioner with task migration for embedded systems implementing DVFS mechanisms and running tasks with real-time constraints. The main novelty is that the proposed policy, namely DP, allowed a single migration at specific points in time.
  11. A scheduler of local and remote memory in computer clusters based on analytical estimations of the system performance according to the overall memory distribution among applications.
  12. A new processor microarchitecture that exploits trace-level parallelism at run-time.
  13. A novel processor microarchitecture ROB-less free with out-of-order retirement of instructions for superscalar processors with noticeable performance improvements over conventional ROB-based processors. The microarchitecture has also been extended for multiprocessor systems.
  14. An in-kernel virtual disk implementation for dynamic caching and I/O scheduling during disk operations.
  15. An effective user-friendly active storage implementation for parallel file systems, in collaboration with the Pacific Northwest National Laboratory (USA).
  16. A new patent on a wireless network localization system (patented in US jointly with Nortel Networks Limited).
  17. A patent of a novel synchronization mechanism for IP networks which considerable improves the accuracy required by network operators (patented in US jointly with Nortel Networks Limited).
  18. A new patent on a method for encoding frames of input video signals, which reduces the computational time needed for encoding a video sequence (patented in US jointly with Florida Atlantic University).
  19. A hardware implementation on FPGA of MPEG-2 to H.264 and DVC to H.264 transcoders, based on previously developed software transcoders, as well as the improvement and optimization of previously proposed algorithms.
  20. Efficient development of video coding algorithms in heterogeneous multicore platforms.
  21. A scalable Crowd Simulation system that allows the simulation of tens of thousands of complex agents, with multiple cameras within the virtual world at interactive frame rates
  22. New schemes of social interactions for intelligent multiagent systems that allow a new level of understanding in crowd behavior prediction. An open-source AgentSpeak (L) library implementing these new decision schemes in Jason
  23. A complete characterization of Distributed Virtual Environments (DVE) based on peer-to-peer architectures and a set of saturation avoidance techniques
  24. Several GPU-accelerated bio inspired algorithms for solving NP-complete problems
  25. A new family of cache coherence protocols for consolidated servers that isolate virtual machines and reduce cache power consumption
  26. A new patent on effective routing in embedded systems (patented in US, Great Britain and Europe jointly with ST Microelectronics).
  27. A first implementation of network-on-chip components in SystemQ, in collaboration with Infineon Technologies AG and Lantiq Deutschland Gmbh
  28. Extension of the coherence domain of AMD Magny-Cours processors beyond the 8-node limit with external logic, including support for HT-Assist
  29. Two new national patents on an augmented reality tool for building construction and machinery industry (patented in Spain jointly with Dragados, S.A.).
  30. A mechanism based on private memory block detection to improve the efficiency of the directory caches and which allows to significantly reduce their size
  31. A design of mapping mechanisms to improve the WiMAX-OFDMA network performance. Moreover, the WiMAX contention process was optimized.
  32. Development of novel collision avoidance mechanism for the IEEE 802.11 multicast service.
  33. A fuzzy-logic-based routing protocol and a novel collision resolution MAC protocol for wireless sensor networks.
  34. An efficient and scalable congestion-management technique for multistage interconnection networks which use distributed-based routing (patent pending)
  35. A hybrid congestion-management technique that combines the dynamic isolation of the flows contributing to congestion with injection throttling at the sources of those flows. This technique has been developed in collaboration with Simula Labs.
  36. New hardware implementations for locks and barriers that reduce execution time and energy consumption in many-core CMPs.
  37. A novel approach to increase concurrency between transactions in Hardware Transactional Memory (HTM) systems that assigns different conflict management policies (eager or lazy) at cache line granularity.
  38. A new disk simulator inside the Linux kernel that allows comparing different I/O mechanisms in parallel and dynamically choosing the best performing one.
  39. Design and implementation of a new OSD device (OSD+) able to manage both data and metadata.
  40. A set of techniques to provide Quality of Service (QoS) to different network technologies, including a formal methodology to provide QoS in InfiniBand subnetworks, a general framework for providing QoS over Advanced Switching networks, and an integrated, cost-effective solution for providing both QoS and congestion management in high-speed interconnection networks.
  41. An indoor positioning system based on RSSI signals able to provide a mean error around 1 meter.
  42. A Power-Token approach that dynamically estimates the processor power consumption at a cycle-level allowing for accurately matching power constraints.
  43. An energy-efficient message management approach based on an address compression scheme that exploits the area slack due to compression for improving the latency of critical messages in CMPs.
  44. A novel pre-fetching mechanism in the context of heterogeneous interconnects that use the low-energy wires for pre-fetching purposes while not degrading performance by using the low-latency wires for critical messages.
  45. A log-based redundant architecture for building fault-tolerant CMP processors by using the capabilities provided by hardware transactional memory (HTM).
  46. A reduced algebraic cost based on epipolar constraints, and its associated minimization algorithm, which has shown to be very efficient for the refinement of incremental multiple view 3D large scale reconstructions. 
  47. An adaptation of standard tensor diagrammatic techniques to the specific requirements of visual geometry, with applications in computation of standard multiview relations (fundamental matrix, trifocal and quadrifocal tensors).
  48. An algorithm for estimation of the full 3D pose of a face in an input video image based on the efficient technique of projective integrals.
  49. Two open source software frameworks designed to reduce programming effort when making research prototypes in the areas of computer vision and image processing, QVision for the C++ programming language (http://qvision.sourceforge.net), and Easyvision for Haskell (https://github.com/albertoruiz/easyVision).
  50. A set of network-aware meta-scheduling heuristic algorithms to improve the QoS of the Grid systems. The autonomic algorithms have been developed to work on-demand and also to perform scheduling in-advance by using simple and efficient predictive techniques.
  51. Development of the SA_Layer (Scheduling in-Advance Layer), an open-source meta-scheduling framework for Grid environments designed to provide the functionality needed to perform meta-scheduling of jobs in advance. The SA-Layer has been implemented as an extension to the GridWay metascheduler and is available for download at (http://www.i3a.uclm.es/raap/gridcloud/SA-Layer/SA-Layer.html).
  52. A technique to determine the geographical position of the nodes composing an air-deployed wireless sensor network.
  53. A set of techniques to determine the contour of physical phenomena, starting from the data gathered by a wireless sensor network.
  54. A straightforward queuing scheme to reduce HoL-blocking in multistage interconnection networks that use the DESTRO routing algorithm.
  55. Virtualization techniques, static and dynamic reconfiguration mechanisms, and fault tolerance support for on-chip-networks